1. Field of the Invention
The present invention relates to a semiconductor device, and, more particularly, to a semiconductor device having a through-hole electrode such as a through-silicon-via (TSV) extending through a semiconductor layer.
2. Description of the Related Art
In a field of information equipment, such as a mobile phone with a camera and a digital camera, miniaturization, integration density, and functionality have all been dramatically improved in recent years. A wafer-level-chip size-package (hereinafter, referred to as a W-CSP), i.e., a package having the same size as a chip, is well-known technology for reducing the size of an image sensor, such as a charge coupled device (CCD) or a Complementary metal oxide semiconductor (CMOS), mounted in such information equipment. W-CSP employs a new package concept in which all fabrication processes are completed in a wafer state. In the same manner as a fine-pitch-ball-grid-array (FBGA), W-CSP is based on an external shape in which terminals are arranged at the bottom surface of the package in the form of, for example, a grid. The size of the package is approximately equal to the size of a chip.
In an image sensor configured in such a W-CSP structure, a through-hole electrode structure such as a through-silicon-via (TSV) structure is adopted so as to improve reliability of a device and to reduce the size of the device. Generally, an electrode, which transmits and receives a signal to and from the outside, of a semiconductor device is formed at the same surface as a circuit element forming surface. In the a through-hole electrode structure, on the other hand, a through hole is formed through a chip from the bottom surface of the chip in the thickness direction of the chip using micro processing technology, a conductive film is formed at the inner wall of the through hole, and the conductive film is connected to a top surface electrode. Consequently, it is possible to achieve input and output of signals at the bottom surface of the chip, which is not generally used. Also, it is possible to stack a plurality of chips using a through-hole electrode technology and to form a signal transmission channel in the stacking direction. As a result, it is possible to reduce a wiring distance, to achieve high-speed operation and high reliability, and to dramatically improve packaging density, as compared with a conventional wiring structure.
FIG. 1 is a view showing the construction of a conventional semiconductor device having a through-hole electrode. Circuit elements 101, such as transistors, are formed at the top surface of a semiconductor substrate 100. An interlayer insulating film 110 is formed on the semiconductor substrate 100. An interlayer insulating film 110 isolates wiring layers 111a and 111b from each other. The lower wiring layer 111a is connected to the upper wiring layer 111b via contact vias 112. An opening is provided in an uppermost interlayer insulating film 110. A top surface electrode 113 is connected to the wiring layer 111b exposed through the opening of the interlayer insulating film 110. A through-hole electrode 130 extends through the semiconductor substrate 100 and the interlayer insulating film 110 such that the through-hole electrode 130 is electrically connected to the wiring layer 111a. A bottom surface wiring 140 is provided on the bottom surface of the semiconductor substrate 100 such that the bottom surface wiring 140 is continuously and integrally formed with the through-hole electrode 130. The bottom surface of the semiconductor substrate 100 is covered with a insulating film 160, such as a solder resist. An opening is provided in the insulating film 160. An external terminal 150 is connected to an exposed portion of the bottom surface wiring 140. The external terminal 150 is electrically connected to the top surface electrode 113 via the bottom surface wiring 140 and the through-hole electrode 130.
The through-hole electrode 130 and the bottom surface wiring 140 are formed, for example, in the following sequence. First, a semiconductor substrate 100 having circuit elements 101 formed thereon is etched from the bottom surface of the semiconductor substrate 100 so as to form a through hole extending to a wiring layer 111a through the semiconductor substrate 100 and an interlayer insulating film 110. Next, a insulating film 120 is formed to cover the inner wall of the through hole, and then only the insulating film 120 formed at the bottom of the through hole is removed to expose the wiring layer 111a at the bottom of the through hole. Next, a barrier layer and a plating seed layer are sequentially formed to cover the side and the bottom of the through hole and the bottom surface of the semiconductor substrate 100. Next, a conductive film made of, for example, Cu is formed to cover the inner wall of the through hole and the bottom surface of the semiconductor substrate 100 using an electroplating method. Subsequently, predetermined patterning is carried out with respect to the conductive film at the bottom surface of the semiconductor substrate 100 so as to form a through-hole electrode 130 and a bottom surface wiring 140. Meanwhile, the inner space of the through hole is filled with a insulating film 160.
A Japanese Patent Application Publication No. 2006-128353 discloses a construction of a semiconductor device having a through-hole electrode.
As described above, the through-hole electrode 130 is integrally formed with the bottom surface wiring 140. The conductive film constituting the through-hole electrode 130 and the conductive film constituting the bottom surface wiring 140 are formed in a single process. For this reason, it is not possible to independently control the film thickness of the conductive film constituting the through-hole electrode 130 and the film thickness of the conductive film constituting the bottom surface wiring 140. As a result, there arise the following problems. That is, if the film thickness of the through-hole electrode which covers the inner wall of the through hole is too large, the conductive film constituting the through-hole electrode is deformed due to thermal stress generated by heat treatment during forming of the film and during forming of an external terminal after forming the film, with the result that the through-hole electrode may be separated from the inner wall of the through hole. The thermal stress is believed to be generated due to a difference of thermal expansion coefficient between the insulating film 160 in the interior of the through-hole electrode 130 and the conductive film constituting the through-hole electrode 130. Consequently, it is not preferable to increase the film thickness of the through-hole electrode such that the film thickness of the through-hole electrode exceeds a predetermined limit due to low durability and low reliability.
On the other hand, the external terminal 150 is connected to the bottom surface wiring 140. In a case in which the bottom surface wiring 140 is made of, for example, Cu, and the external terminal 150 is made of, for example, SnAg, Cu of the bottom surface wiring 140 may melt into Sn of the external terminal 150 during a reflow process carried out when the semiconductor device is mounted on a mounting substrate, with the result that a void may be generated, and therefore, the bottom surface wiring 140 may be separated from the bottom surface of the semiconductor substrate 100. In a conventional manufacturing method, the film thickness of the bottom surface wiring 140 is restricted if the film thickness of the through-hole electrode 130 is restricted. In a case in which the film thickness of the bottom surface wiring 140 is small, therefore, most of the bottom surface wiring 140 may be eroded by an alloy layer, with the result that a possibility of separation of the bottom surface wiring 140 is further increased. Consequently, it is preferable for the bottom surface wiring 140 to have a sufficient film thickness at least a connection potion with the external terminal 150. Meanwhile, mutual diffusion between the bottom surface wiring 140 and the external terminal 150 may occur in a combination of Cu and SnPb, Cu and AuSn, or Al and Au in addition to a combination of Cu and SnAg as described above.
In the conventional manufacturing method as described above, the through-hole electrode 130 and the bottom surface wiring 140 are continuously and integrally formed with each other, and the through-hole electrode 130 and the bottom surface wiring 140 are formed in a single process, with the result that the film thickness of one of the through-hole electrode 130 and the bottom surface wiring 140 affects the film thickness of the other. In a case in which the film thickness of the through-hole electrode 130 is too large, therefore, separation of the through-hole electrode 130 may occur. Also, in a case in which the film thickness of the bottom surface wiring 140 is too small, separation of the bottom surface wiring 140 may occur. In the conventional manufacturing method, it is difficult to avoid these problems simultaneously.